Platform-based IC (integrated circuit) design is a powerful concept for coping with the increased pressure on time-to-market, design and manufacturing costs encountered in the current IC market. A platform is a large-scale, high-complexity semiconductor device that includes one or more of the following elements: (1) memory; (2) a customizable array of transistors; (3) an IP (intellectual property) block; (4) a processor, e.g., an ESP (embedded standard product); (5) an embedded programmable logic block; and (6) interconnect. RapidChip™ developed by LSI Logic Corp. is an instance of a platform. The basic idea behind the platform-based design is to avoid designing and manufacturing a chip from scratch. Some portion of the chip's architecture is predefined for a specific type of application. Through extensive design reuse, the platform-based design may provide faster time-to-market and reduced design cost.
Under a platform approach, there are two distinct steps entailed in creating a final end-user product: a prefabrication step and a customization step. In a prefabrication step, a slice is built on a wafer. A slice is a pre-manufactured chip in which all silicon layers have been built, leaving the metal layers or top metal layers to be completed with the customer's unique IP. For example, RapidSlice™ developed by LSI Logic Corp. is an instance of a slice. One or more slices may be built on a single wafer. It is understood that a slice may include one or more bottom metal layers or may include no metal layers at all. In a preferred embodiment of the prefabrication step, portions of the metal layers are pre-specified to implement the pre-defined blocks of the platform and the diffusion processes are carried out in a wafer fab. The base characteristics, in terms of the IP, the processors, the memory, the interconnect, the programmable logic and the customizable transistor array, are all pre-placed in the design and pre-diffused in the slice. However, a slice is still fully decoupled because the customer has not yet introduced the function into the slice. In a customization step, the customer-designed function is merged with the pre-defined blocks and the metal layers (or late-metal components) are laid down, which couple the elements that make up the slice built in the wafer fab, and the customizable transistor array is configured and given its characteristic function. In other embodiments, early-metal steps may be part of the pre-fabricated slice to reduce the time and cost of the customization step, resulting in a platform which is more coupled and specific. It is understood that a prefabrication step and a customization step may be performed in different foundries. For example, a slice may be manufactured in one foundry. Later, in a customization step, the slice may be pulled from inventory and metalized, which gives the slice its final product characteristics in a different foundry.
At the stage of synthesis for VLSI (Very Large-Scale Integration) designs, it is well known that memories typically have a much higher defect density than other logic. As a result, memories require comprehensive testing. One conventional method for memory testing is to use a Memory Built-In Self Test (Mem-BIST) controller, which is placed on a chip close to the memory under test, to perform testing in the test mode (see FIG. 3).
In platform-based design, there are often tens or even hundreds of memories on a chip. The conventional method of placing one Mem-BIST controller for each memory instance may result in an unwanted increase in the chip area. On the other hand, a platform (e.g., RapidChip™) often includes multiple instances of a single memory type or module. Thus, it is desired to share one Mem-BIST controller for all instances of each memory type. However, connecting a Mem-BIST controller to multiple instances of a single memory type directly may lead to long propagation delays along with long wires, thereby decreasing the test frequency (see FIG. 5).
Thus, it is desirable to provide a new method and BIST architecture for fast memory testing in a platform-based integrated circuit, which may increase test frequency of multiple instances of a single memory type.